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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21365-1E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F73SP
s DESCRIPTION
The Fujitsu MB15F73SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2000 MHz prescaler and a 600 MHz prescaler. A 64/65 or a 128/129 for the 2000 MHz prescaler, and a 8/9 or a 16/17 for the 600 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. MB15F73SP has the same configuration with MB15F03 or MB15F03L. The BiCMOS process is used , as a result a supply current is typically 3.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data. The new package (BCC20) decreases an area of MB15F73SP more than 30 % comparing with the former BCC16 (for dual PLL). MB15F73SP is ideally suited for wireless mobile communications, such as PDC.
s FEATURES
: RF synthesizer : 2000 MHz max : IF synthesizer : 600 MHz max * Low power supply voltage : VCC = 2.4 to 3.6 V * Ultra Low power supply current : ICC = 3.5 mA typ. (VCC = Vp = 2.7 V, Ta = +25C, SWIF = SWRF = 0 in IF/RF locking state) (Continued) * High frequency operation
s PACKAGES
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M04)
MB15F73SP
(Continued) * Direct power saving function: Power supply current in power saving mode Typ. 0.1 A (VCC = Vp = 2.7 V, Ta = +25C) Max. 10 A (VCC = Vp = 2.7 V) * Software selectable charge pump current: 1.5 mA/6.0 mA typ. * Dual modulus prescaler: 2000 MHz prescaler (64/65 or128/129 )/600 MHz prescaler (8/9 or 16/17) * 23 bit shift register * Serial input binary 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit * On-chip phase control for phase comparator * Built-in digital locking detector circuit to detect PLL locking and unlocking * Operating temperature: Ta = -40 to +85C * Sireal data format compatible with MB15F02SL
s PIN ASSIGNMENTS
(TSSOP-20) TOP VIEW (BCC-20) TOP VIEW
OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DoIF LD/fout
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Clock Data LE finRF XfinRF GNDRF VCCRF PSRF VpRF DoRF
OSCIN Data GND Clock finIF XfinIF GNDIF VCCIF PSIF VpIF 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 12 9 10 11 LE finRF XfinRF GNDRF VCCRF PSRF
DoIF DoRF LD/fout VpRF
(FPT-20P-M06)
(LCC-20P-M04)
2
MB15F73SP
s PIN DESCRIPTION
Pin no. TSSOP BCC 1 2 3 4 5 6 19 20 1 2 3 4 Pin name OSCIN GND finIF XfinIF GNDIF VCCIF I/O I Descriptions The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit), the shift register and the oscillator input buffer. Power saving mode control for the IF-PLL section. This pin must be set at "L" Power-On. (Open is prohibited.) PSIF = "H" ; Normal mode / PSIF = "L" ; Power saving mode Charge pump output for the IF-PLL section. Look detect signal output (LD)/ phase comparator monitoring output (fout). The output signal is selected by a LDS bit in a serial data. LDS bit = "H" ; outputs fout signal / LDS bit = "L" ; outputs LD signal Charge pump output for the RF-PLL section. Power saving mode control for the RF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited. ) PSRF = "H" ; Normal mode / PSRF = "L" ; Power saving mode Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit). Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connection to an external VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock.
Ground for OSC input buffer and the shift register circuit. I I
Ground for the IF-PLL section. I
7 8 9 10 11 12 13
5 6 7 8 9 10 11
PSIF VpIF DoIF LD/fout DoRF VpRF PSRF
Power supply voltage input pin for the IF-PLL charge pump. O O O
Power supply voltage input pin for the RF-PLL charge pump. I
14 15 16 17
12 13 14 15
VCCRF GNDRF XfinRF finRF
Ground for the RF-PLL section. I I
18
16
LE
I
19
17
Data
I
20
18
Clock
I
3
MB15F73SP
s BLOCK DIAGRAM
VCCIF (4) 6 GNDIF 5 (3) VpIF 8 (6)
PSIF 7 (5)
Intermittent mode control (IF-PLL)
3 bit latch
LDS SWIF FCIF
7 bit latch
11 bit latch
fpIF
Phase comp. (IF-PLL)
Binary 7-bit Binary 11-bit swallow counter programable (IF-PLL) counter (IF-PLL)
Charge Current pump Switch (IF-PLL)
9 DoIF (7)
finIF 3 (1) XfinIF 4 (2)
Prescaler (IF-PLL) (8/9, 16/17)
Lock Det. (IF-PLL)
2 bit latch
14 bit latch
Binary 14-bit programmable ref. counter(IF-PLL)
1 bit latch C/P setting counter
LDIF
T1
T2
frIF OSCIN 1 (19) frRF T1 OR
2 bit latch
AND
C/P setting counter
1 bit latch
T2
Binary 14-bit programmable ref. counter(RF-PLL) 14 bit latch
Selector LD frIF 10 LD/ frRF ( 8 ) fout fpIF fpRF
( 15 ) finRF 17 XfinRF 16 ( 14 )
Prescaler (RF-PLL) (64/65, 128/129)
Lock Det. (RF-PLL)
PSRF 13 (11)
Intermittent mode control (RF-PLL)
LDS SWRF FCRF
Binary 11-bit Binary 7-bit swallow counter programmable counter(RF-PLL) (RF-PLL)
Phase comp. (RF-PLL)
Charge Current pump Switch (RF-PLL)
11 DoRF (9)
3 bit latch
7 bit latch
11 bit latch
fpRF
LE 18 ( 16 ) ( 17 ) Data 19 Clock 20 ( 18 )
Schmitt circuit
Latch selector
Schmitt circuit Schmitt circuit
CC NN 12
23-bit shift register
2 ( 20 ) GND
( 12 ) 14 VCCRF
15 ( 13 ) GNDRF
12 ( 10 ) VpRF
O -- TSSOP ( ) -- BCC 4
MB15F73SP
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature LD/fout Do Symbol VCC Vp VI VO VDO Tstg Rating Min. -0.5 VCC -0.5 GND GND -55 Max. 4.0 4.0 VCC + 0.5 VCC Vp +125 Unit V V V V V C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCC Vp VI Ta Value Min. 2.4 VCC GND -40 Typ. 2.7 2.7 Max. 3.6 3.6 VCC +85 Unit V V V C
Power supply voltage Input voltage Operating temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F73SP
s ELECTRICAL CHARACTERISTICS
*
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Parameter Power supply current Power saving current finIF *3 Operating frequency finRF finIF finRF
*3
Symbol ICCIF *1 ICCRF
*2
Condition IF PLL RF PLL PSIF = PSRF = "L" PSIF = PSRF = "L" IF PLL RF PLL IF PLL, 50 system RF PLL, 50 system Schmitt triger input Schmitt triger input
Value Min. 50 100 3 -15 -15 0.5 0.7 VCC + 0.4 0.7 VCC -1.0 -1.0 0 -100 VCC - 0.4 1.0 Typ. 1.3 2.2 0.1
*8
Max. 10 10 600 2000 40 +2 +2 VCC 0.3 VCC - 0.4 0.3 VCC +1.0 +1.0 +100 0 0.4 0.4 2.5 -1.0
Unit mA mA A A MHz MHz MHz dBm dBm VP-P V V V V A A A A V V V V nA mA mA
IPSIF IPSRF finIF finRF fOSC PfinIF PfinRF VOSC VIH VIL VIH VIL IIH *4 IIL *4 IIH IIL *4 VOH VOL VDOH VDOL IOFF IOH *4 IOL
0.1 *8
OSCIN Input sensitivity
Input available voltage OSCIN "H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current Data LE Clock PSIF PSRF Data LE Clock PS OSCIN
"H" level output voltage LD/ "L" level output voltage fout "H" level output voltage DoIF "L" level output voltage DoRF High impedance cutoff DoIF current DoRF "H" level output current LD/ "L" level output current fout
VCC = Vp = 2.7 V, IOH = -1 mA VCC = Vp = 2.7 V, IOL = 1 mA VCC = Vp = 2.7 V, IDOL = 0.5 mA VCC = Vp = 2.7 V VOFF = 0.5 V to Vp - 0.5 V VCC = Vp = 2.7 V VCC = Vp = 2.7 V
VCC = Vp = 2.7 V, IDOH = -0.5 mA Vp - 0.4
(Continued)
6
MB15F73SP
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Symbol Condition VCC = Vp = 2.7 V, VDOH = Vp / 2, Ta = +25 C VCC = Vp = 2.7 V, VDOL = Vp / 2, Ta = +25 C VDO = Vp / 2 0.5 V VDO Vp - 0.5 V -40 C Ta 85 C, VDO = Vp / 2 CS bit = "H" CS bit = "L" CS bit = "H" CS bit = "L" Value Min. Typ. -6.0 -1.5 6.0 1.5 3 10 10 Max. Unit mA mA mA mA % % %
Parameter "H" level output current "L" level output current DoIF DoRF DoIF DoRF
IDOH *4
IDOL
IDOL/IDOH IDOMT *5 Charge pump current rate vs VDO vs Ta IDOVD
*6
IDOTA *7
*1 : finIF = 480 MHz, fosc = 12.8 MHz, VCCIF = VpIF = 2.7 V, SWIF = 0, Ta = + 25 C, in locking state. *2 : finRF = 2000 MHz, fosc = 12.8 MHz, VCCRF = VpRF = 2.7 V, SWRF = 0, Ta = + 25 C, in locking state. *3 :AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency. *4 : The symbol "-" (minus) means direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = + 25 C (||I3| - |I4||) / [ (|I3| + |I4|) / 2 ] x 100 (%) *6 : VCC = Vp = 2.7 V, Ta = + 25 C (Applied to each IDOL, IDOH) [ (||I2| - |I1||) / 2 ] / [ (|I1| + |I2|) / 2 ] x 100 (%) *7 : VCC = Vp = 2.7 V, Ta = + 25 C (Applied to each IDOL, IDOH) [ ||IDO (85C) | - |IDO (-40C) || / 2 ] / [ |IDO (85C) | + |IDO (-40C) | / 2 ] x 100 (%) *8 : fosc = 12.8 MHz, VCCRF = VpRF = VCCIF = VpIF = 2.7 V, Ta = + 25 C
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vp/2 Vp - 0.5 Vp
Charge pump output voltage (V)
7
MB15F73SP
s FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [(P x N) + A] x fOSC / R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. The programmable The programmable reference counter reference counter for the IF-PLL for the RF-PLL CN1 CN2 0 0 1 0 The programmable counter and the swallow counter for the IF-PLL 0 1 The programmable counter and the swallow counter for the RF-PLL 1 1
(1) Shift Register Configuration * Programmable Reference Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23 X X X
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
CS R1 to R14 T1, 2 CN1, 2 X
: Charge pump current select bit : Divide ratio setting bits for the programmable reference counter (3 to 16,383) : Test purpose bit : Control bit : Dummy bits (Set "0" or "1")
Note : Data input with MSB first.
8
MB15F73SP
* Programmable Counter
(LSB)
Data Flow
(MSB)
1
CN1
2
CN2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
LDS SWIF/RF FCIF/RF A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
A1 to A7 N1 to N11 LDS SWIF/RF FCIF/RF CN1, 2
: Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF) : Phase control bit for the phase detector (IF: FCIF, RF: FCRF) : Control bit
Note : Data input with MSB first. (2) Data setting * Binary 14-bit Programmable Reference Counter Data Setting Divide ratio 3 4 * * * 16383 R14 R13 R12 R11 R10 R9 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 R8 0 0 * * * 1 R7 0 0 * * * 1 R6 0 0 * * * 1 R5 0 0 * * * 1 R4 0 0 * * * 1 R3 0 1 * * * 1 R2 1 0 * * * 1 R1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9 3 4 * * * 2047 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 N8 0 0 * * * 1 N7 0 0 * * * 1 N6 0 0 * * * 1 N5 0 0 * * * 1 N4 0 0 * * * 1 N3 0 1 * * * 1 N2 1 0 * * * 1 N1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited * Binary 7-bit Swallow Counter Data Setting Divide ratio 0 1 * * * 127 A7 0 0 * * * 1 A6 0 0 * * * 1 A5 0 0 * * * 1 A4 0 0 * * * 1 A3 0 0 * * * 1 A2 0 0 * * * 1 A1 0 1 * * * 1
9
MB15F73SP
* Prescaler Data Setting Divide ratio Prescaler divide ratio IF-PLL Prescaler divide ratio RF-PLL * Charge Pump Current Setting Current value 6.0 mA 1.5 mA CS 1 0 SW = "H"
8/9
SW = "L"
16/17 128/129
64/65
* LD/fout Output Select Data Setting LD/fout output signal fout signals LD signal LDS 1 0
* Test Purpose Bit Setting LD/fout pin state Outputs frIF. Outputs frRF. Outputs fpIF. Outputs fpRF. T1 0 1 0 1 T2 0 0 1 1
* Phase Comparator Phase Switching Data Setting Phase comparator input fr > fp fr < fp fr = fp Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High
(1)
FCIF, RF = "H" DoIF, RF H L Z
FCIF, RF = "L" DoIF, RF L H Z
(1) VCO polarity FC = "H" (2) VCO polarity FC = "L"
VCO Output Frequency
(2)
LPF Output voltage
Max.
Note : Give attention to the polarity for using active type LPF.
10
MB15F73SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status Normal mode Power saving mode PS pin
H L
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the single PLL, the lock detector, LD, remains high, indicating a locked condition. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Note : When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1s. Note : PS pin must be set "L" for Power-ON.
OFF
ON tV 1 s
VCC Clock Data LE PS
tPS 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS : L H) 100 ns later after setting serial data.
11
MB15F73SP
4. SERIAL DATA INPUT TIMING
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 1st data
Invalid data
2nd data
Control bit
Data
MSB
LSB
Clock
t1 t7 t2 t5 t4
LE
t3 t6
Parameter t1 t2 t3 t4
Min. 20 20 30 20
Typ.
Max.
Unit ns ns ns ns
Parameter t5 t6 t7
Min. 30 100 100
Typ.
Max.
Unit ns ns ns
Note : LE should be "L" when the data is transferred into the shift register.
12
MB15F73SP
s PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H DoIF/RF Z L
(FC bit = Low)
DoIF/RF Z L H
* LD Output Logic IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
LD output H L L L
Notes :* Phase error detection range = -2 to +2 * Pulses on DoIF/RF signals during locking state are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCIN input frequency as follows. tWU > 2/fosc: e.g. tWU > 156.3 ns when fosc = 12.8 MHz tWU < 4/fosc: e.g. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F73SP
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF VpIF 0.1 F VCCIF 0.1 F 1000 pF 50 S.G.
1000 pF S.G.
LD/fout 10
DoIF 9
VpIF 8
PSIF 7
VCCIF 6
GNDIF 5
XfinIF 4
finIF 3
GND 2
OSCIN 1
50
11 DoRF
12 VpRF
13 PSRF
14 VCCRF
15 GNDRF
16 XfinRF
17 finRF
18 LE
19 Data
20 Clock
1000 pF
Controller (divide ratio setting)
1000 pF VpRF 0.1 F VCCRF 0.1 F 50 S.G.
Note : The terminal number shows that of TSSOP-20.
14
MB15F73SP
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity - Input frequency
10.0
Input sensitivity PfinRF (dBm)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 0
,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 500 1000 1500 2000 2500
Input frequency finRF (MHz)
IF-PLL input sensitivity - Input frequency
10.0
Input sensitivity PfinIF (dBm)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0
,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 0 100 200 300 400 500 600 700
Input frequency finIF (MHz)
15
MB15F73SP
2. OSCIN input sensitivity
Input sensitivity - Input frequency
10 0 -10 -20 -30 -40 -50 -60 0 20 40 60 80 100 120 140 160 180 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 200 220
Input sensitivity VCO (dBm)
,,,, ,,,,
SPEC
Ta = +25 C
Input frequency fOSC (MHz)
16
MB15F73SP
3. RF-PLL Do output current
* 1.5 mA mode IDO - VDO
10.0
Charge pump output current IDO (mA)
Ta = +25 C VCC = Vp = 2.7 V
IDOL 0.0 IDOH
-10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
* 6.0 mA mode IDO - VDO
10.0 Ta = +25 C VCC = Vp = 2.7 V IDOL
Charge pump output current IDO (mA)
0.0
IDOH -10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
17
MB15F73SP
4. IF-PLL Do output current
* 1.5 mA mode
IDO - VDO
10.0 Ta = +25 C VCC = Vp = 2.7 V
Charge pump output current IDO (mA)
IDOL 0.0 IDOH
-10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
* 6.0 mA mode
IDO - VDO
10.0 Ta = +25 C VCC = Vp = 2.7 V IDOL
Charge pump output current IDO (mA)
0.0
IDOH -10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
18
MB15F73SP
5. fin input impedance
finIF input impedance
4 : 17.262 -115.55 2.2956 pF 600.000 000 MHz 1 : 669.97 -1.0088 k 50 MHz 2 : 72.875 -351.75 200 MHz 3 : 27.047 -178.02 400 MHz
1 2 4 3
START 50.000 000 MHz
STOP 600.000 000 MHz
finRF input impedance
4 : 13.596 -5.6699 14.035 pF 2 000.000 000 MHz 1 : 289.69 -647.06 100 MHz 2 : 12.887 -65.199 1 GHz 3 : 11.751 -30.16 1.5 GHz 4 1
3 2 START 100.000 000 MHz STOP 2 000.000 000 MHz
19
MB15F73SP
6. OSCIN input impedance
OSCIN input impedance
4 : 31.813 -679.69 2.3416 pF 100.000 000 MHz 1 : 12.425 k -10.812 k 3 MHz 2: 524 -3.3809 k 20 MHz 3 : 128.94 -1.7113 k 40 MHz
4 3 1 2
START 3.000 000 MHz
STOP 100.000 000 MHz
20
MB15F73SP
s REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit S.G. OSCIN Do fin 10 k Spectrum Analyzer VCO 3900 pF 4.1 k 0.047 F 3300 pF LPF fVCO = 1624 MHz KV = 22 MHz/V fr = 10 kHz fOSC = 19.68 MHz LPF VCC = 3.0 V VVCO = 3.0 V Ta = + 25 C CP : 6 mA mode
* PLL Reference Leakage
ATTEN 10 dB RL 0 dBm VAVG 25 10 dB/ MKR -70.00 dB 10.0 kHz
MKR D 10.0 kHz S -70.00 dB
CENTER 1.6240000 GHz VBW 300 Hz RBW 300 Hz
SPAN 100.0 kHz SWP 2.80 sec
* PLL Phase Noise
ATTEN 10 dB RL 0 dBm VAVG 20 10 dB/ MKR -43.00 dB 1.18 kHz
MKR D 1.18 kHz S -43.00 dB
CENTER 1.62400000 GHz VBW 100 Hz RBW 100 Hz
SPAN 10.00 kHz SWP 802 ms
(Continued)
21
MB15F73SP
(Continued)
PLL Lock Up time 953 MHz981 MHz within 1 kHz L chH ch 4.822 ms
PLL Lock Up time 981 MHz953 MHz within 1 kHz H chL ch 4.956 ms
1.646004500 GHz
1.624004750 GHz
1.646000500 GHz
1.624000750 GHz
1.645996500 GHz -2.178 ms T1 489 s
2.822 ms 7.822 ms 1.000 ms/div 4.822 ms T2 5.311 ms
1.623996750 GHz -2.178 ms T1 489 s
2.822 ms 7.822 ms 1.000 ms/div 4.956 ms T2 5.444 ms
22
MB15F73SP
s APPLICATION EXAMPLE
OUTPUT
VCO 1000 pF 2.7 V 1000 pF
LPF 2.7 V 0.1 F 0.1 F
from controller
Clock 20
DATA 19
LE 18
finRF 17
XfinRF 16
GNDRF 15
VCCRF 14
PSRF 13
VpRF 12
DoRF 11
MB 15F73SP 1 OSCIN 2 GND 3 finIF 4 XfinIF 5 GNDIF 6 VCCIF 7 PSIF 8 VpIF 9 DoIF 10 LD/fout
Lock Det. 1000 pF 1000 pF 1000 pF 2.7 V 2.7 V
0.1 F TCXO OUTPUT VCO
0.1 F
LPF
Note *Clock, Data, LE : Schmitt trigger circuit is provided(insert a pull-down or pull-up registor to prevent oscillation when open-circuite in the input). *The terminal number shows that of TSSOP-20.
23
MB15F73SP
s USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must equal equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device
s ORDERING INFORMATION
Part number MB15F73SPPFT MB15F73SPPV Package 20-pin plastic TSSOP (FPT-20P-M06) 20-pad plastic BCC (LCC-20P-M04) Remarks
24
MB15F73SP
s PACKAGE DIMENSIONS
20-pin plastic SSOP (FPT-20P-M06)
6.42/6.78(.253/.267) 6.500.10(.256.004)
20 11
"A"
4.400.10 (.173.004) INDEX
6.400.10 (.252.004)
4.80(.189) MAX
5.400.18 (.213.007)
Details of "A" part 1.050.05 (.041.002)
1 10
5 -5
+3
0.65(.026) TYP
0.22 -0.07 .009 -.003
+0.03 +.006
0.50(.020) 0.070.03 (.003.001)
0.10(.004)
0.415(.016)
0.980.02 (.039.001)
C
1998 FUJITSU LIMITED F20026S-1C-1
Dimensions in mm (inches)
(Continued)
25
MB15F73SP
(Continued)
20-pad plastic BCC (LCC-20P-M04)
3.600.10(.142.004)
16 11
3.00(.118)TYP 0.80(.031)MAX (Mounting height)
11
0.250.10 (.010.004)
16
0.250.10 (.010.004) INDEX AREA 3.400.10 (.134.004) 2.70(.106) TYP "D" "A" "B" "C"
0.50(.020) TYP
1
6
6
1
0.0850.04 (.003.002) (Stand off)
0.50(.020) TYP 2.80(.110)REF
0.05(.002)
Details of "A" part 0.500.10 (.020.004)
Details of "B" part 0.500.10 (.020.004)
Details of "C" part 0.500.10 (.020.004) C0.20(.008)
Details of "D" part 0.300.10 (.012.004)
0.600.10 (.024.004)
0.300.10 (.012.004)
0.600.10 (.024.004)
0.400.10 (.016.004)
C
1999 FUJITSU LIMITED C20055S-1C-1
Dimensions in mm (inches)
26
MB15F73SP
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F9911 (c) FUJITSU LIMITED Printed in Japan

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